The invention described herein relates generally to semiconductor device fabrication utilizing lithographic masks. In particular, the invention relates to the detection of significant defects on lithographic masks
Fabricating semiconductor devices such as logic and memory devices typically includes processing a substrate such as a semiconductor wafer using a number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example lithography is a semiconductor fabrication process that involves transferring a pattern from a mask to a resist arranged on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing, etching, deposition, and ion implantation. Multiple semiconductor devices may be fabricated in an arrangement on a semiconductor wafer and then separated into individual semiconductor devices.
Lithography is typically one of the most important processes in integrated circuit manufacturing since this is the process in which features are patterned on the wafer. The pattern printed in a resist by lithography is then utilized as a masking layer to transfer the pattern to one or more layers on the wafer in subsequent processing steps. Therefore, the pattern that is formed on the wafer during lithography directly affects the features of the integrated circuits that are formed on the wafer. Consequently, defects that are formed on the wafer during lithography may be particularly problematic for the integrated circuit manufacturing process. One of the many ways in which defects may be formed on the patterned wafer during lithography is by transfer of defects that are present on the mask to the wafer. Therefore, detection and correction of defects on the mask such as unwanted particulate or other matter is performed rather stringently to prevent as many defects on the mask from being transferred to the wafer during lithography.
However, as the dimensions of integrated circuits decrease and the patterns being transferred from the mask to the wafer become more complex, defects or marginalities in the features formed on the mask become increasingly important. In particular, if the pattern is not correctly formed on the mask, such discrepancies increasingly produce defects on the wafer as the dimension of the pattern decrease and the complexity of the pattern increases. That is, marginalities in the mask pattern may cause problems in the pattern that is printed on the wafer. Therefore, significant efforts have been devoted to methods and systems that can be used to detect problems in the pattern on the mask or in the design that will cause problems on the wafer. These efforts are relatively complex and difficult due, at least in part, to the fact that not all discrepancies or marginalities in the pattern formed on the mask (as compared to the ideal pattern) will cause errors on the wafer that will adversely affect the integrated circuit. In other words, some error in the pattern formed on the mask may not produce defects on the wafer at all or may produce defects on the wafer that will not reduce the performance characteristics of the integrated circuit.
Accordingly, improved mechanisms for detecting defects on a mask that would cause problems or variations on the patterned wafer are needed.